Memory device with a common source line masking circuit

具有公共源极线屏蔽电路的存储器设备

Abstract

本公开涉及具有公共源极线屏蔽电路的存储器设备。所述存储器设备包括多个存储器瓦块,每个瓦块包括局部公共源极线(CSL)板、多个位线和多个字线,每个耦接到多个存储器单元;和屏蔽电路,耦接到每个存储器瓦块,以用于基于全局公共源极线控制是否升高局部CSL板和多个位线。
The disclosure relates to a memory device with a common source line masking circuit. The memory device comprises: a plurality of memory tiles, each tile comprising a local common source line (CSL) plate, a plurality of bit lines and a plurality of word lines, each coupled to a plurality of memory cells; and a masking circuit, coupled to each of the memory tiles, for controlling whether to raise the local CSL plate and the plurality of bit lines based on the a global common source line.

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Patent Citations (3)

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